Hikeda, A 3D packaging with 4 Gb chip-stacked DRAM and 3Gbps high-speed logic, in 3D-SIC 2007, International 3D-System Integration Conference 2007, Tokyo, Japan (2007) Brodersen (eds.), Low Power CMOS Design (Kluwer Academic Publishers, Boston, 1995) Annaratone, Digital CMOS Circuit Design (Kluwer Academic Publishers, Boston, 1986)Ī. Campardo et al., An overview of Flash architectural developments. Ravasio, Error Correction Codes for Non-volatile Memories (Springer, Dordrecht, 2008) Novosel, VLSI-Design of Non-volatile Memories (Springer, New York, 2005) Marelli, Inside NAND Flash Memories (Springer, New York, 2010) Micheloni et al., A 4 Gb 2b/cell NAND Flash memory with embedded 5b BCH ECC for 36 MB/s system read throughput, in IEEE International Solid-State Circuits Conference 2006, Digest of Technical Papers, ISSCC 2006, Feb 2006, pp. This process is experimental and the keywords may be updated as the learning algorithm improves. These keywords were added by machine and not by the authors. Incremental Step Pulse Programming (ISPP).In the NAND array, transferring the regulated high voltages to the gate of the memory cell. This circuit has the task of properly biasing each single wordline All these circuits are described in the High Voltage Management In multilevel storage, cell’s gate biasing voltages need to be very accurate and voltage regulatorsīecome a must. Therefore, charge pumps are used to generate all the needed voltages within the chip. Programming and erasing floating gate cells require voltages higher than the chip power supply. Counting the number of electrons in the floating gate is definitely one of the most challenging task, considering that has to be performed with few transistors: sensing techniques are described in Sect. , who is in charge of running all the internal algorithms, to the fast DDR interface. First of all, we describe the logic part of the chip, from the embedded microcontroller Of a NAND memory, we guide the reader through the main building blocks. All these operations require a mix of analog and digital circuits that need to be properly and timely driven. When we program, erase or read, electrons must be injected, extracted and counted, respectively. The information stored in each memory cell is fully analog because it is related to the number of electrons stored in the floating gate. This chapter focuses on design aspects of NAND chips. A Solid-State-Disk is made up by a Flash controllerĭevices.

Plash design